Display panel

ABSTRACT

A display panel includes a substrate and many driving chips. The substrate has many pad regions located in a non-display region of the substrate. Each pad region has many first pins with the same length disposed therein, and a pin pitch between two adjacent first pins, a width of each of the first pins, or both the pin pitch and the width vary with the positions where the first pins are disposed in the corresponding pad region. The driving chips are disposed in the non-display region of the substrate. Each driving chip has many second pins, and each second pin is electrically connected to each first pin correspondingly.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of an application Ser. No.11/828,346, filed on Jul. 25, 2007, now allowed, which claims thepriority benefit of Taiwan application serial no. 96107982, filed onMar. 8, 2007. The entirety of each of the above-mentioned patentapplications is hereby incorporated by reference herein and made a partof this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a display panel, and more particularly relatesto a display panel in which pins of a chip can be accurately bonded topins of a substrate.

2. Description of Related Art

With prominent display quality and low costs, cathode ray tube (CRT)displays have dominated the display market in recent years. However, theCRT display not only produces hazardous radiation but also occupies alarge space. Recently, thanks to rapid development in the semiconductordevices, planar displays having the advantages of high definition, greatspace utilization efficiency, low power consumption and non-radiationhave become the mainstream products in the display market.

The planar display is consisted of a display panel, a light source forproviding sufficient luminance to the display panel, and driving chipsdisposed on a substrate of the display panel. The driving chips areemployed to drive circuits within the display panel, such that thedisplay panel is capable of displaying images.

FIG. 1A is a schematic view of a conventional display panel, while FIG.1B is an enlarged partial view of FIG. 1A. Referring to FIG. 1, aplurality of pad regions 120 is disposed in a non-display region 110 aof a substrate 110 in a display panel 100, and a plurality of pins 122is disposed in each of the pad regions 120. The pins 122 areelectrically connected to pins 132 of driving chips 130.

However, due to material properties of the pins 122 and 132, when thepins 132 of the driving chips 130 and the pins 122 in each of the padregions 120 are bonded through implementing a thermal compressionprocess, the pins 122 may encounter quality issues related to shapedeformation, positional deviation, etc. According to different positionswhere the pins 122 are disposed in the pad region 120. All the issuesresult in imperfect bonding of the pins 132 of the driving chips 130 tothe pins 122 in each of the pad regions 120. As a bonding rate of thepins 132 of the driving chips 130 to the pins 122 on the substrate 110is rather low, the display quality of the display panel 100 is thengreatly impaired.

SUMMARY OF THE INVENTION

The invention is directed to a display panel having driving chipsdisposed thereon. The driving chips have pins which can be accuratelybonded to the pins on the display panel.

The invention provides a display panel including a substrate and aplurality of driving chips. The substrate has a plurality of pad regionslocated in a non-display region of the substrate, and a plurality offirst pins with the same length is disposed in each of the pad regions.A pin pitch between the two adjacent first pins, a width of each of thefirst pins, or both said pin pitch and said width vary with differentpositions where the first pins are disposed in a corresponding padregion. The driving chips are disposed in the non-display region of thesubstrate. Here, each of the driving chips has a plurality of secondpins, and each second pin is electrically connected to each first pincorrespondingly.

According to one embodiment of the invention, each of the pad regionsincludes a non expansion region and two expansion regions at two sidesof the non expansion region.

According to one embodiment of the invention, each pin pitch between thetwo adjacent first pins in the non expansion region is the same.

According to one embodiment of the invention, the pin pitch between thetwo adjacent first pins in the expansion region is increased in adirection away from the adjoining non expansion region.

According to one embodiment of the invention, the width of each of thefirst pins in the expansion region is increased in the direction awayfrom the adjoining non expansion region.

According to one embodiment of the invention, the width of each of thefirst pins in the non expansion region is the same.

According to one embodiment of the invention, the pin pitch between thetwo adjacent first pins in the expansion region is increased in thedirection away from the adjoining non expansion region.

According to one embodiment of the invention, the width of each of thefirst pins in the expansion region is increased in the direction awayfrom the adjoining non expansion region.

According to one embodiment of the invention, each pin pitch between thetwo adjacent first pins in the expansion region is the same.

According to one embodiment of the invention, the pin pitch between thetwo adjacent first pins in the non expansion region is increased in adirection away from the adjoining expansion region.

According to one embodiment of the invention, the width of each of thefirst pins in the non expansion region is increased in the directionaway from the adjoining expansion region.

According to one embodiment of the invention, the width of each of thefirst pins in the expansion region is the same.

According to one embodiment of the invention, the pin pitch between thetwo adjacent first pins in the non expansion region is increased in thedirection away from the adjoining expansion region.

According to one embodiment of the invention, the width of each of thefirst pins in the non expansion region is increased in the directionaway from the adjoining expansion region.

According to one embodiment of the invention, the substrate is an activedevice array substrate.

In the display panel provided by the invention, the width of each of thefirst pins, the pin pitch between the two first pins, or both said widthand said pin pitch may vary with different positions where the firstpins are disposed in one of the pad regions. Thus, after a thermalcompression process is performed to bond the driving chips to thesubstrate, the first pins and the second pins can be bonded at a betterbonding rate than the bonding rate disclosed in the related art, andyield of the display panel can be improved as well.

In order to make the aforementioned and other features and advantages ofthe invention more comprehensible, several embodiments accompanied withfigures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic view of a conventional display panel.

FIG. 1B is an enlarged partial view of FIG. 1A.

FIG. 2A is a schematic view of a display panel according to a firstembodiment of the invention.

FIG. 2B is an enlarged partial view of a substrate of the display paneldepicted in FIG. 2A.

FIG. 2C is a schematic view depicting a bonding of first pins of asubstrate to second pins of driving chips in a pad region.

FIG. 3 is a schematic view depicting a bonding of first pins of asubstrate to second pins of driving chips in a display panel accordingto a second embodiment of the invention.

FIG. 4 is a schematic view depicting a bonding of first pins of asubstrate to second pins of driving chips in a display panel accordingto a third embodiment of the invention.

FIG. 5A is a schematic view of a display panel according to a fourthembodiment of the invention.

FIG. 5B is an enlarged partial view of a substrate of the display paneldepicted in FIG. 5A.

FIG. 5C is a schematic view depicting a bonding of first pins of asubstrate to second pins of driving chips in a pad region.

FIG. 6 is a schematic view of a display panel according to a fifthembodiment of the invention.

FIG. 7 is a schematic view of a display panel according to a sixthembodiment of the invention.

FIG. 8 is a schematic view of a display panel according to a seventhembodiment of the invention.

FIG. 9 is a schematic view of a display panel according to an eighthembodiment of the invention.

FIG. 10 is a schematic view of a display panel according to a ninthembodiment of the invention.

FIG. 11 is a schematic view of a display panel according to a tenthembodiment of the invention.

FIG. 12 is a schematic view of a display panel according to an eleventhembodiment of the invention.

FIG. 13 is a schematic view of a display panel according to a twelfthembodiment of the invention.

FIG. 14 is a schematic view of a display panel according to a thirteenthembodiment of the invention.

FIG. 15 is a schematic view of a display panel according to a fourteenthembodiment of the invention.

FIG. 16 is a schematic view of a display panel according to a fifteenthembodiment of the invention.

DESCRIPTION OF EMBODIMENTS First Embodiment

FIG. 2A is a schematic view of a display panel according to a firstembodiment of the invention, while FIG. 2B is an enlarged partial viewof a substrate of the display panel depicted in FIG. 2A. Referring toFIGS. 2A and 2B together, a display panel 2000 of the present embodimentincludes a substrate 2100 and a plurality of driving chips 2200. Thesubstrate 2100 of the present embodiment is an active device arraysubstrate, and the substrate 2100 has a display region 2120 and anon-display region 2140 surrounding the display region 2120. A pluralityof pad regions 2142 is disposed in the non-display region 2140, and eachof the pad regions 2142 has a center line 2142 a. In addition, aplurality of first pins 2144 with the same length is disposed in each ofthe pad regions 2142, and the first pins 2144 are symmetrically arrangedwith respect to the center line 2142 a in the pad region 2144 inparallel.

It should be noted that a pin pitch between the two adjacent first pins2144 in each of the pad regions 2142 of the display panel 2000 may varywith different positions where the first pins 2144 are disposed in oneof the pad regions 2142. More particularly, the pin pitch between thetwo adjacent first pins 2144 may be increased in a direction away fromthe center line 2142 a.

FIG. 2C is a schematic view depicting a bonding of the first pins of thesubstrate to second pins of driving chips in the pad region. A pluralityof driving chips 2200 is disposed in the non-display region 2140. Eachof the driving chips 2200 has a plurality of second pins 2220, and eachsecond pin 2220 is electrically connected to each first pin 2144.

As the driving chips 2200 are disposed on the substrate 2100 throughperforming a thermal compression process, the second pins 2220 of thedriving chips 2200 are electrically connected to the first pins 2144 inone of the pad regions 2142. However, during the thermal compressionprocess, the first pins 2144 and the second pins 2220 are easilyexpanded by heat due to material properties of the first pins 2144 andthe second pins 2220.

It should be noted that an arrangement of the pin pitch between the twoadjacent first pins 2144 can be calculated and obtained through anN^(th) degree equation with one unknown as follows. Y=aX^(n)+bX¹+c.Here, X refers to an input, Y denotes an output, and a, b and c areconstants. On the other hand, bounding conditions (B.Cs.) are providedhereinafter.

B.C.1:

-   -   X=the 0^(th) first pin    -   Y=pin pitch=Y1

B.C.2:

-   -   X=the X1^(th) first pin    -   Y=pin pitch=Y2

B.C.3:

-   -   Y′(0)=0

The above B.Cs are substituted into the equation, and an effectiveequation Y=(Y2-Y1)*(X/X1)^(n)+Y1 is obtained.

By substituting the X1^(th) first pin 2144 into said effective equation,it can be deduced that the pin pitch between the two adjacent first pins2144 is increased in a direction away from the center line 2142 a.Besides, the thermal expansion results in the imperfect bonding of thefirst pins 2144 to the second pins 2220. Since the pin pitch between thetwo adjacent first pins 2144 is increased in the direction away from thecenter line 2142 a, the imperfect bonding can then be improved, so as toincrease the bonding rate of the first pins 2144 to the second pins 2220after the thermal compression process is carried out.

In comparison with the related art, the high bonding rate of the firstpins 2144 to the second pins 2220 in the present embodiment leads to asaving in reworking material costs arisen from the imperfect bonding ofthe first pins 2144 to the second pins 2220, and rework labor hours canalso be reduced, simultaneously increasing yield of the display panel2000.

People in this field should be able to develop a better modeling of theequation or favorably adjust the B.Cs. After the embodiments and theclaims of the invention are studied, a better modeling of the equationmay be developed and the corresponding B.C. may be revised based onactual manufacturing process and demands. For example, Y may also be thewidth of the first pins 2144. A theory provided by the followingembodiments is similar to the concept of the invention. In other words,the N^(th) N degree equation with one unknown can be used to establishthe effective equations for each of the following embodiments, and thusno further description will be provided hereinafter.

Second Embodiment

The present embodiment is approximately identical to the firstembodiment, and same or similar reference numbers used in the presentembodiment and in the first embodiment represent the same or the likeelements. Accordingly, no further description thereof is providedhereinafter. On the other hand, the difference between the presentembodiment and the first embodiment will be demonstrated as follows.

FIG. 3 is a schematic view depicting a bonding of first pins of asubstrate to second pins of driving chips in a display panel accordingto a second embodiment of the invention. Referring to FIG. 3, thedifference between the present embodiment and the first embodiment liesin that a width of each of first pins 3144 in each of pad regions 3142in a display panel of the present embodiment (not shown) may vary withdifferent positions where the first pins 3144 are disposed in thecorresponding pad region 3142. Particularly, the first pins 3144 arearranged with respect to a center line 3142 a of the pad region 3142,and the width of each of the first pins 3144 is increased in a directionaway from the center line 3142 a.

Thereby, with the increase in the width of each of the first pins 3144in the pad region 3142 in the direction away from the center line 3142a, the imperfect bonding which is caused by a thermal expansion andoccurs between the first pins 3144 and second pins 3220 can be improvedafter a thermal compression process is performed.

In comparison with the related art, the high bonding rate of the firstpins 3144 to the second pins 3220 in the present embodiment leads to asaving in reworking material costs arisen from the imperfect bonding ofthe first pins 3144 to the second pins 3220, and rework labor hours canalso be reduced, simultaneously increasing yield of the display panel(not shown).

Third Embodiment

The present embodiment is approximately identical to the first and thesecond embodiments, and same or similar reference numbers used in thepresent embodiment and in the first and the second embodiments representthe same or the like elements. Accordingly, no further descriptionthereof is provided hereinafter. FIG. 4 is a schematic view depicting abonding of first pins of a substrate to second pins of driving chips ina display panel according to a third embodiment of the invention.Referring to FIG. 4, the difference between the present embodiment andthe first and the second embodiments lies in that both a pin pitchbetween two adjacent first pins 4144 in each of pad regions 4142 in adisplay panel (not shown) and a width of each of the first pins 4144 mayvary with different positions where the first pins 4144 are disposed inthe corresponding pad region 4142. Particularly, the first pins 4144 arearranged with respect to a center line 4142 a of the pad region 4142,and the width of each of the first pins 4144 and the pin pitch betweenthe two adjacent first pins 4144 are both increased in a direction awayfrom the center line 4142 a.

Thus, the imperfect bonding which is caused by a thermal expansion andoccurs between the first pins 4144 and second pins 4220 according to therelated art can be improved after a thermal compression process isperformed, increasing the bonding rate of the first pins 4144 to thesecond pins 4220. Accordingly, reworking material costs arisen from theimperfect bonding of the first pins 4144 to the second pins 4220 can besaved, and rework labor hours can also be decreased, simultaneouslyincreasing yield of the display panel (not shown).

Besides, with the increase in the width of each of the first pins 4144and in the pin pitch between the two adjacent first pins 4144 in thedirection away from the center line 4142 a, the display panel of thepresent embodiment gives a better yield than the display panels of thefirst and the second embodiments.

Fourth Embodiment

The present embodiment is approximately identical to the firstembodiment, and same or similar reference numbers used in the presentembodiment and in the first embodiment represent the same or the likeelements. Accordingly, no further description thereof is providedhereinafter. FIG. 5A is a schematic view of a display panel according toa fourth embodiment of the invention. FIG. 5B is an enlarged partialview of a substrate of the display panel depicted in FIG. 5A. FIG. 5C isa schematic view depicting a bonding of first pins of a substrate tosecond pins of driving chips in a pad region. Referring to FIGS. 5A, 5Band 5C together, a display panel 5000 of the present embodiment includesa substrate 5100 and a plurality of driving chips 5200. The substrate5100 has a display region 5120 and a non-display region 5140 surroundingthe display region 5120. A plurality of pad regions 5142 is disposed inthe non-display region 5140, and each of the pad regions 5142 can befurther divided into a non expansion region 5142 a and two expansionregions 5142 b at two sides of the non expansion region 5142 a. Inaddition, the first pins 5144 in each of the pad regions 5142 have thesame length and width, and the first pins 5144 are arranged in parallel.

It should be noted that each pin pitch between the two adjacent firstpins 5144 in the non expansion region 5142 a is the same, while the pinpitch between the two adjacent first pins 5144 in the expansion regions5142 b may vary with different positions where the first pins 5144 aredisposed relative to the non expansion region 5142 a.

More particularly, as the first pins 5144 are relatively disposed in afarther distance from the non expansion region 5142 a, the pin pitchbetween the two adjacent first pins 5144 in the expansion regions 5142 bis increased.

Moreover, a plurality of driving chips 5200 is disposed in thenon-display region 5140. Each of the driving chips 5200 has a pluralityof second pins 5220, and each second pin 5220 is electrically connectedto each first pin 5144.

Referring to FIG. 5B, when the driving chips 5200 are disposed on thesubstrate 5100 through performing a thermal compression process, thesecond pins 5220 of the driving chips 5200 are electrically connected tothe first pins 5144 in one of the pad regions 5142. However, during thethermal compression process, the first pins 5144 and the second pins5220 are easily expanded by heat due to the material properties of thefirst pins 5144 and the second pins 5220.

It should be noted that the pin pitch between the two adjacent firstpins 5144 in the expansion regions 5142 b is increased when the firstpins 5144 are relatively disposed in a farther distance from the nonexpansion region 5142 a. Thus, the imperfect bonding which is caused bya thermal expansion and occurs between the first pins 5144 and thesecond pins 5220 can be improved after a thermal compression process isperformed, increasing the bonding rate of the first pins 5144 to thesecond pins 5220.

In comparison with the related art, the high bonding rate of the firstpins 5144 to the second pins 5220 in the present embodiment leads to asaving in reworking material costs arisen from the imperfect bonding ofthe first pins 5144 to the second pins 5220, and rework labor hours canalso be reduced, simultaneously increasing yield of the display panel5000.

Fifth Embodiment

The present embodiment is approximately identical to the fourthembodiment, and same or similar reference numbers used in the presentembodiment and in the fourth embodiment represent the same or the likeelements. Accordingly, no further description thereof is providedhereinafter. FIG. 6 is a schematic view depicting a bonding of firstpins of a substrate to second pins of driving chips in a display panelaccording to a fifth embodiment of the invention. Referring to FIG. 6,the difference between the present embodiment and the fourth embodimentlies in that a width of each of the first pins 6144 in expansion regions6142 b may vary with different positions where the first pins 6144 aredisposed relative to a non expansion region 6142 a.

More particularly, as the first pins 6144 are relatively disposed in afarther distance from the non expansion region 6142 a, the width of eachof the first pins 6144 in the expansion regions 6142 b is increased.

Thus, as second pins 6220 are electrically connected to the first pins6144 through performing a thermal compression process, the imperfectbonding which is caused by a thermal expansion and occurs between thefirst pins 6144 and the second pins 6220 can be improved after a thermalcompression process is performed, increasing the bonding rate of thefirst pins 6144 to the second pins 6220.

In comparison with the related art, the high bonding rate of the firstpins 6144 to the second pins 6220 in the present embodiment leads to asaving in reworking material costs arisen from the imperfect bonding ofthe first pins 6144 to the second pins 6220, and rework labor hours canalso be reduced, simultaneously increasing yield of the display panel(not shown).

Sixth Embodiment

The present embodiment is approximately identical to the fourth and thefifth embodiments, and same or similar reference numbers used in thepresent embodiment and in the fourth and the fifth embodiments representthe same or the like elements. Accordingly, no further descriptionthereof is provided hereinafter. FIG. 7 is a schematic view depicting abonding of first pins of a substrate to second pins of driving chips ina display panel according to a sixth embodiment of the invention.Referring to FIG. 7, the difference between the present embodiment andthe fourth and the fifth embodiments lies in that both a width of eachof the first pins 7144 in expansion regions 7142 b and a pin pitchbetween the two adjacent first pins 7144 may vary with differentpositions where the first pins 7144 are disposed relative to a nonexpansion region 7142 a.

More particularly, as the first pins 7144 are relatively disposed in afarther distance from the non expansion region 7142 a, the width of eachof the first pins 7144 in the expansion regions 7142 b is increased.Further, as the first pins 7144 are relatively disposed in a fartherdistance from the non expansion region 7142 a, the pin pitch between thetwo adjacent first pins 7144 in the expansion regions 7142 b isincreased.

Thus, as second pins 7220 are electrically connected to the first pins7144 through performing a thermal compression process, the imperfectbonding which is caused by a thermal expansion and occurs between thefirst pins 7144 and the second pins 7220 can be improved after a thermalcompression process is performed, increasing the bonding rate of thefirst pins 7144 to the second pins 7220.

In comparison with the related art, the high bonding rate of the firstpins 7144 to the second pins 7220 in the present embodiment leads to asaving in reworking material costs arisen from the imperfect bonding ofthe first pins 7144 to the second pins 7220, and rework labor hours canalso be reduced, simultaneously increasing yield of the display panel(not shown).

Besides, the display panel of the present embodiment has a higherbonding rate than the display panels provided by the fourth and thefifth embodiments.

Seventh Embodiment

The present embodiment is approximately identical to the fourth thefifth and the sixth embodiments, and same or similar reference numbersused in the present embodiment and in the fourth, the fifth and thesixth embodiments represent the same or the like elements. Accordingly,no further description thereof is provided hereinafter. FIG. 8 is aschematic view of a display panel according to a seventh embodiment ofthe invention. Referring to FIG. 8, the difference between the presentembodiment and the fourth, the fifth and the sixth embodiments lies inthat a width of each of the first pins 8144 in a non expansion region8142 a is the same, while a pin pitch between the two adjacent firstpins 8144 in expansion regions 8142 b may vary with different positionswhere the first pins 8144 are disposed relative to the non expansionregion 8142 a.

More particularly, as the first pins 8144 are relatively disposed in afarther distance from the non expansion region 8142 a, the pin pitchbetween the two adjacent first pins 8144 in the expansion regions 8142 bis increased.

Eighth Embodiment

The present embodiment is approximately identical to the seventhembodiment, and same or similar reference numbers used in the presentembodiment and in the seventh embodiment represent the same or the likeelements. Accordingly, no further description thereof is providedhereinafter. FIG. 9 is a schematic view of a display panel according toan eighth embodiment of the invention. Referring to FIG. 9, thedifference between the present embodiment and the seventh embodimentlies in that a width of each of the first pins 9144 in expansion regions9142 b may vary with different positions where the first pins 9144 aredisposed relative to a non expansion region 9142 a.

More particularly, as the first pins 9144 are relatively disposed in afarther distance from the non expansion region 9142 a, the width of eachof the first pins 9144 in the expansion regions 9142 b is increased.

Ninth Embodiment

In the present embodiment, the seventh and the eighth embodiments areboth applied. People skilled in the art can easily combine and applysaid embodiments, and thus further descriptions are briefly providedhereinafter. FIG. 10 is a schematic view of a display panel according toa ninth embodiment of the invention. As shown in FIG. 10, in the presentembodiment, both a width of each of the first pins 10144 in a expansionregions 10142 b and a pin pitch between the two adjacent first pins10144 may vary with different positions where the first pins 10144 aredisposed relative to a non expansion region 10142 a.

More particularly, as the first pins 10144 are relatively disposed in afarther distance from the non expansion region 10142 a, the width ofeach of the first pins 10144 in the expansion regions 10142 b isincreased. Further, as the first pins 10144 are relatively disposed in afarther distance from the non expansion region 10142 a, the pin pitchbetween the two adjacent first pins 10144 in the expansion regions 10142b is increased.

Tenth Embodiment

The present embodiment is approximately identical to the seventhembodiment, and same or similar reference numbers used in the presentembodiment and in the seventh embodiment represent the same or the likeelements. Accordingly, no further description thereof is providedhereinafter. FIG. 11 is a schematic view depicting a bonding of firstpins of a substrate to second pins of driving chips in a display panelaccording to a tenth embodiment of the invention. Referring to FIG. 11,the difference between the present embodiment and the seventh embodimentlies in that each pin pitch between the two adjacent first pins 11144 inexpansion regions 11142 b is the same, while a width of each of thefirst pins 11144 in a non expansion region 11142 a may vary withdifferent positions where the first pins 11144 are disposed relative tothe expansion regions 11142 b.

More particularly, as the first pins 11144 are relatively disposed in afarther distance from the expansion regions 11142 b, the pin pitchbetween the two adjacent first pins 11144 in the non expansion region11142 a is increased.

Eleventh Embodiment

The present embodiment is approximately identical to the tenthembodiment, and same or similar reference numbers used in the presentembodiment and in the tenth embodiment represent the same or the likeelements. Accordingly, no further description thereof is providedhereinafter. FIG. 12 is a schematic view of a display panel according toan eleventh embodiment of the invention. Referring to FIG. 12, thedifference between the present embodiment and the tenth embodiment liesin that a width of each of the first pins 12144 in a non expansionregion 12142 a may vary with different positions where the first pins12144 are disposed relative to expansion regions 12142 b.

More particularly, as the first pins 12144 are relatively disposed in afarther distance from the expansion regions 12142 b, the width of eachof the first pins 12144 in the non expansion region 12142 a isincreased.

Twelfth Embodiment

In the present embodiment, the tenth and the eleventh embodiments areboth applied. People skilled in the art can easily combine and applysaid embodiments, and thus further descriptions are briefly providedhereinafter. FIG. 13 is a schematic view of a display panel according toa twelfth embodiment of the invention. As shown in FIG. 13, in thepresent embodiment, both a width of each of the first pins 13144 in anon expansion region 13142 a and a pin pitch between the two adjacentfirst pins 13144 may vary with different positions where the first pins13144 are disposed relative to expansion regions 13142 b.

More particularly, as the first pins 13144 are relatively disposed in afarther distance from the expansion regions 13142 b, the width of eachof the first pins 13144 in the non expansion region 13142 a isincreased. Further, as the first pins 13144 are relatively disposed in afarther distance from the expansion regions 13142 b, the pin pitchbetween the two adjacent first pins 13144 in the non expansion region13142 a is increased.

Thirteenth Embodiment

The present embodiment is approximately identical to the tenthembodiment, and same or similar reference numbers used in the presentembodiment and in the tenth embodiment represent the same or the likeelements. Accordingly, no further description thereof is providedhereinafter. FIG. 14 is a schematic view of a display panel according toa thirteenth embodiment of the invention. Referring to FIG. 14, thedifference between the present embodiment and the tenth embodiment liesin that a width of each of the first pins 14144 in expansion regions14142 b is the same, while a pin pitch between the two adjacent firstpins 14144 may vary with the positions where the first pins 14144 aredisposed relative to a non expansion region 14142 a. Further, the pinpitch between the two adjacent first pins 14144 in the non expansionregion 14142 a may vary with the positions where the first pins 14144are disposed relative to the expansion regions 14142 b.

More particularly, as the first pins 14144 are relatively disposed in afarther distance from the expansion regions 14142 b, the pin pitchbetween the two adjacent first pins 14144 in the non expansion region14142 a is increased.

Fourteenth Embodiment

The present embodiment is approximately identical to the thirteenthembodiment, and same or similar reference numbers used in the presentembodiment and in the thirteenth embodiment represent the same or thelike elements. Accordingly, no further description thereof is providedhereinafter. FIG. 15 is a schematic view of a display panel according toa fourteenth embodiment of the invention. Referring to FIG. 15, thedifference between the present embodiment and the thirteenth embodimentlies in that a width of each of the first pins 15144 in a non expansionregion 15142 a may vary with different positions where the first pins15144 are disposed relative to expansion regions 15142 b.

More particularly, as the first pins 15144 are relatively disposed in afarther distance from the expansion regions 15142 b, the width of eachof the first pins 15144 in the non expansion region 15142 a isincreased.

Fifteenth Embodiment

In the present embodiment, the thirteenth and the fourteenth embodimentsare both applied. People skilled in the art can easily combine and applysaid embodiments, and thus further descriptions are briefly providedhereinafter. FIG. 16 is a schematic view depicting a bonding of firstpins of a substrate to second pins of driving chips in a display panelaccording to a fifteenth embodiment of the invention. As shown in FIG.16, in the present embodiment, both a width of each of the first pins16144 in a non expansion region 16142 a and a pin pitch between the twoadjacent first pins 16144 may vary with different positions where thefirst pins 16144 are disposed relative to expansion regions 16142 b.

More particularly, as the first pins 16144 are relatively disposed in afarther distance from the expansion regions 16142 b, the width of eachof the first pins 16144 in the non expansion region 16142 a isincreased. Further, as the first pins 16144 are relatively disposed in afarther distance from the expansion regions 16142 b, the pin pitchbetween the two adjacent first pins 16144 in the non expansion region16142 a is increased.

All of the above fifteen embodiments take an increasing width of thefirst pins or an increasing pin pitch between the two adjacent firstpins for example. However, it should be noted that people skilled in theart are able to easily combine, change and apply said embodiments and itwill still be considered within the spirit of the invention after theclaims and the embodiments of the invention are studied.

Based on the above, in the display panel of the invention, the width ofeach of the first pins of the substrate and the pin pitch between thetwo first pins may vary with different positions at which the first pinsare disposed in one of the pad regions. Therefore, when the second pinsof the driving chips are bonded to the first pins through performing thethermal compression process, the second pins and the first pins canstill be accurately bonded to each other in spite of the thermalexpansion. In comparison with the related art, the display panelprovided by the invention has a higher bonding rate.

Furthermore, as the bonding rate of the pins in the display panel isincreased, yield of the display panel is improved as well.Simultaneously, the reworking material costs can be saved, and therework labor hours and costs are further reduced.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of theinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the invention covermodifications and variations of this invention provided they fall withinthe scope of the following claims and their equivalents.

1. A display panel, comprising: a substrate having a plurality of padregions located in a non-display region of the substrate, wherein aplurality of first pins with the same length is disposed in each of thepad regions, and a pin pitch between the two adjacent first pins, awidth of each of the first pins, or both said pin pitch and said widthvary with the positions where the first pins are disposed in acorresponding pad region; and a plurality of driving chips disposed inthe non-display region of the substrate, wherein each of the drivingchips has a plurality of second pins, and each second pin iselectrically connected to each first pin.
 2. The display panel of claim1, wherein each of the pad regions comprises a non expansion region andtwo expansion regions at two sides of the non expansion region.
 3. Thedisplay panel of claim 2, wherein each pin pitch between the twoadjacent first pins in the non expansion region is the same.
 4. Thedisplay panel of claim 3, wherein the pin pitch between the two adjacentfirst pins in the expansion region is increased in a direction away fromthe adjoining non expansion region.
 5. The display panel of claim 3,wherein the width of each of the first pins in the expansion region isincreased in the direction away from the adjoining non expansion region.6. The display panel of claim 2, wherein the width of each of the firstpins in the non expansion region is the same.
 7. The display panel ofclaim 6, wherein the pin pitch between the two adjacent first pins inthe expansion region is increased in the direction away from theadjoining non expansion region.
 8. The display panel of claim 6, whereinthe width of each of the first pins in the expansion region is increasedin the direction away from the adjoining non expansion region.
 9. Thedisplay panel of claim 2, wherein each pin pitch between the twoadjacent first pins in the expansion region is the same.
 10. The displaypanel of claim 9, wherein the pin pitch between the two adjacent firstpins in the non expansion region is increased in a direction away fromthe adjoining expansion region.
 11. The display panel of claim 9,wherein the width of each of the first pins in the non expansion regionis increased in the direction away from the adjoining expansion region.12. The display panel of claim 9, wherein the width of each of the firstpins in the expansion region is the same.
 13. The display panel of claim12, wherein the pin pitch between the two adjacent first pins in the nonexpansion region is increased in the direction away from the adjoiningexpansion region.
 14. The display panel of claim 12, wherein the widthof each of the first pins in the non expansion region is increased inthe direction away from the adjoining expansion region.